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Microchip Technology /ATSAME70Q20 /PWM0 /IDR1

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Interpret as IDR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHID0)CHID0 0 (CHID1)CHID1 0 (CHID2)CHID2 0 (CHID3)CHID3 0 (FCHID0)FCHID0 0 (FCHID1)FCHID1 0 (FCHID2)FCHID2 0 (FCHID3)FCHID3

Description

PWM Interrupt Disable Register 1

Fields

CHID0

Counter Event on Channel 0 Interrupt Disable
CHID1

Counter Event on Channel 1 Interrupt Disable
CHID2

Counter Event on Channel 2 Interrupt Disable
CHID3

Counter Event on Channel 3 Interrupt Disable
FCHID0

Fault Protection Trigger on Channel 0 Interrupt Disable
FCHID1

Fault Protection Trigger on Channel 1 Interrupt Disable
FCHID2

Fault Protection Trigger on Channel 2 Interrupt Disable
FCHID3

Fault Protection Trigger on Channel 3 Interrupt Disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data